FW82801EB Intel, FW82801EB Datasheet - Page 645

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 204. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Primary/Secondary IDE
Timing
Slave IDE Timing
Synchronous DMA Control
Register
Synchronous DMA Timing
Register
IDE I/O Configuration
Register
PCI Power Management
Capability ID
PCI Power Management
Capabilities
PCI Power Management
Control and Status
Message Signaled Interrupt
Capability ID
Message Signaled Interrupt
Message Control
Message Signaled Interrupt
Message Address
Message Signaled Interrupt
Message Data
Address Map
Port Status and Control
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
®
Register Name
ICH5 PCI Configuration Registers (Sheet 7 of 11)
4Ah – 4Bh
40h – 43h
2E – 2Fh
70 – 71h
72 – 73h
74 – 77h
80 – 81h
82 – 83h
84 – 87h
88 – 89h
00 – 01h
02 – 03h
04 – 05h
06 – 07h
Offset
3Ch
3Dh
34h
44h
48h
54h
90h
92h
08h
09h
UHCI Controller (D29:F0/F1/F2/F3)
Section 11.1.16, “SID—Subsystem Identification Register
(SATA–D31:F2)” on page 440
Section 11.1.17, “CAP—Capabilities Pointer Register (SATA–
D31:F2)” on page 441
Section 11.1.18, “INT_LN—Interrupt Line Register (SATA–
D31:F2)” on page 441
Section 11.1.19, “INT_PN—Interrupt Pin Register (SATA–
D31:F2)” on page 441
Section 11.1.20, “IDE_TIM — IDE Timing Register (SATA–
D31:F2)” on page 442
Section 11.1.21, “SIDETIM—Slave IDE Timing Register (SATA–
D31:F2)” on page 444
Section 11.1.22, “SDMA_CNT—Synchronous DMA Control
Register (SATA–D31:F2)” on page 445
Section 11.1.23, “SDMA_TIM—Synchronous DMA Timing
Register (SATA–D31:F2)” on page 446
Section 11.1.24, “IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2)” on page 447
Section 11.1.25, “PID—PCI Power Management Capability
Identification Register (SATA–D31:F2)” on page 448
Section 11.1.26, “PC—PCI Power Management Capabilities
Register (SATA–D31:F2)” on page 448
Section 11.1.27, “PMCS—PCI Power Management Control and
Status Register (SATA–D31:F2)” on page 449
Section 11.1.28, “MID—Message Signaled Interrupt Identifiers
Register (SATA–D31:F2)” on page 449
Section 11.1.29, “MC—Message Signaled Interrupt Message
Control Register (SATA–D31:F2)” on page 450
Section 11.1.30, “MA—Message Signaled Interrupt Message
Address Register (SATA–D31:F2)” on page 450
Section 11.1.31, “MD—Message Signaled Interrupt Message
Data Register (SATA–D31:F2)” on page 450
Section 11.1.32, “MAP—Address Map Register (SATA–D31:F2)”
on page 451
Section 11.1.33, “PCS—Port Control and Status Register
(SATA–D31:F2)” on page 451
Section 12.1.1, “VID—Vendor Identification Register (USB—
D29:F0/F1/F2/F3)” on page 462
Section 12.1.2, “DID—Device Identification Register (USB—
D29:F0/F1/F2/F3)” on page 462
Section 12.1.3, “PCICMD—PCI Command Register (USB—
D29:F0/F1/F2/F3)” on page 462
Section 12.1.4, “PCISTS—PCI Status Register (USB—D29:F0/
F1/F2/F3)” on page 463
Section 12.1.5, “RID—Revision Identification Register (USB—
D29:F0/F1/F2/F3)” on page 463
Section 12.1.6, “PI—Programming Interface Register (USB—
D29:F0/F1/F2/F3)” on page 464
Datasheet Section and Location
Register Index
645