FW82801EB Intel, FW82801EB Datasheet - Page 157

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.13.9.2
Intel
®
Table 68. Transitions Due to RI# Signal
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled
Note: Filtering/Debounce on RI# will not be done in ICH5. Can be in modem or external.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine should
unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this case, the
transition to the G2/S5 state should not depend on any particular response from the processor
(e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.
New: A power button override forces a transition to S5, even if PWROK is not active
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
4-second timer starts counting when the ICH5 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event.
Once the system has resumed to the S0 state, the 4-second timer starts.
by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it is conceivable that the
user will press and continue to hold the Power Button waiting for the system to awake. Since a
4-second press of the Power Button is already defined as an Unconditional Power down, the power
button timer will be forced to inactive while the power-cycle timer is in progress. Once the
power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4#
power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the
Override condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button.
It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in
an S5 state, the Power Button can wake the system, but the Sleep Button cannot.
Although the ICH5 does not include a specific signal designated as a Sleep Button, one of the
GPIO signals can be used to create a “Control Method” Sleep Button. See the Advanced
Configuration and Power Interface, Version 2.0b for implementation details.
RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.
when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH5
generates an interrupt based on RI# active, and the interrupt will be set up as a Break event.
Present State
S1–S5
S0
RI# Active
RI# Active
Event
RI_EN
X
0
1
Wake Event
Ignored
Ignored
Event
Functional Description
Table 68
.
shows
157