FW82801EB Intel, FW82801EB Datasheet - Page 151

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.13.6.1
5.13.6.2
5.13.7
5.13.7.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The ICH5 asserts STPCLK# to
throttle the processor clock. After a programmable time, the ICH5 deasserts STPCLK# and the
processor appears to return to the C0 state. This allows the processor to operate at reduced average
power, with a corresponding decrease in performance. Two methods are included to start throttling:
Throttling due to the THRM# signal has higher priority than the software initiated throttling.
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
Sleep States
Sleep State Overview
The ICH5 directly supports different sleep states (S1–S5), which are entered by setting the
SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several
assumptions:
Transition Rules among S0/Cx and Throttling States
1. Software enables a timer with a programmable duty cycle. The duty cycle is set by the
2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
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THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as
Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of
switching power supplies.
unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to
Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and
system. The Thermal Override condition will end when THRM# goes inactive.
Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because
the processor can only perform one register access at a time and Sleep states have higher
priority than thermal throttling.
When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit can be
internally treated as being disabled (no throttling while going to sleep state). Note that thermal
throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the
SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5
states).
Level 2 C2 Level 2 Level 2 C2 Level 2 C2 The Host controller must post Stop-Grant cycles in
such a way that the processor gets an indication of the end of the special cycle prior to the
ICH5 observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for
a sufficient period after the processor observes the response phase.
Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the
processor can only perform one register access at a time. A request to Sleep always has higher
priority than throttling.
Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note
that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal
throttling (since S1–S5 sleep state has higher priority).
The G3 state cannot be entered via any software mechanism. The G3 state indicates a
complete loss of power.
Functional Description
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