FW82801EB Intel, FW82801EB Datasheet - Page 256

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.22.2.1
5.22.2.2
5.22.2.3
256
Output Slot 0: Tag Phase
Output Slot 1: Command Address Port
AC-Link Output Frame (SDOUT)
A new output frame begins with a low to high transition of AC_SYNC. AC_SYNC is synchronous
to the rising edge of AC_BIT_CLK. On the immediately following falling edge of AC_BIT_CLK,
the codec samples the assertion of AC_SYNC. This falling edge marks the time when both sides of
AC-link are aware of the start of a new frame. On the next rising edge of AC_BIT_CLK, the ICH5
transitions AC_SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit
position is presented to the AC-link on a rising edge of AC_BIT_CLK, and subsequently sampled
by the codec on the following falling edge of AC_BIT_CLK. This sequence ensures that data
transitions and subsequent sample points for both incoming and outgoing data streams are time
aligned.
The output frame data phase corresponds to the multiplexed bundles of all digital output data
targeting codec DAC inputs and control registers. Each output frame supports up to twelve
outgoing data time slots. The ICH5 generates 16 or 20 bits and stuffs remaining bits with 0s.
The output data stream is sent with the most significant bit first, and all invalid slots are stuffed
with 0s. When mono audio sample streams are output from the ICH5, software must ensure both
left and right sample stream time slots are filled with the same data.
Slot 0 is considered the tag phase. The tag phase is a special,16-bit time slot wherein each bit
conveys a valid tag for its corresponding time slot within the current frame. A 1 in a given bit
position of slot 0, indicates that the corresponding time slot within the current frame has been
assigned to a data stream and contains valid data. If a slot is tagged invalid with a 0 in the
corresponding bit position of slot 0, the ICH5 stuffs the corresponding slot with 0s during that
slot’s active time.
Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire
frame. If the valid frame bit is set to 1, this indicates that the current frame contains at least one slot
with valid data. When there is no transaction in progress, the ICH5 deasserts the frame valid bit.
Note that after a write to slot 12, that slot will always stay valid, and therefore the frame valid bit
remains set.
The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time
slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between
separate codecs on the link.
Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted
across the link at its fixed 48 kHz frame rate. The codec can control the output sample rate of the
ICH5 using the SLOTREQ bits as described in the AC ’97 v2.3 Specification
The command port is used to control features and monitor status of AC ’97 functions including, but
not limited to, mixer settings and power management. The control interface architecture supports
up to 64, 16-bit read/write registers, addressable on even byte boundaries. Only the even registers
(00h, 02h, etc.) are valid. Output frame slot 1 communicates control register address, and write/
read command information.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet