FW82801EB Intel, FW82801EB Datasheet - Page 283

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

7.1.17
7.1.18
7.1.19
7.1.20
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
MAX_LAT — Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
Bit
7:0
Bit
7:0
Bit
7:0
Bit
7:0
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s interrupt
request is connected to PIRQA#. However, in the Intel
controller interrupt is generated PIRQE# will go active, not PIRQA#. Note that if the PIRQE# signal
is used as a GPIO, the external visibility will be lost (though PIRQE# will still go active internally).
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in increments of 0.25 µs)
that the LAN controller needs to retain ownership of the PCI bus when it initiates a transaction.
Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of 0.25 µs) the
LAN controller needs to access the PCI bus.
Capability ID (CAP_ID)
controller supports PCI power management.
3Dh
01h
3Eh
08h
3Fh
38h
DCh
01h
—
RO. Hardwired to 01h to indicate that the Intel
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
®
ICH5 implementation, when the LAN
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
®
ICH5’s integrated LAN
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