FW82801EB Intel, FW82801EB Datasheet - Page 139

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.11.3
5.11.4
5.11.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
configuration space. If the locking bits are set, the corresponding range in the RAM will not be
readable or writable. A write cycle to those locations will have no effect. A read cycle to those
locations will not return the location’s actual value (may be all 0s or all 1s).
Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS
and allow it to relock the RAM range.
Century Rollover
The ICH5 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form
99 to 00. Upon detecting the rollover, the ICH5 sets the NEWCENTURY_STS bit (TCOBASE +
04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update
registers in the RTC RAM that are associated with century value. If the system is in a sleep state
(S1
SMI# is generated. When the system resumes from the sleep state, BIOS should check the
NEWCENTURY_STS bit and update the century value in the RTC RAM.
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an ICH5-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
Using RTCRST# to clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of
those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to
ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the
RTC power well will be set to their default state. BIOS can monitor the state of this bit, and
manually clear the RTC CMOS array once the system is booted. The normal position would cause
RTCRST# to be pulled up through a weak pull-up resistor.
their default state when RTCRST# is asserted.
–
S5) when the century rollover occurs, the ICH5 also sets the NEWCENTURY_STS bit, but no
Table 53
shows which bits are set to
Functional Description
139