FW82801EB Intel, FW82801EB Datasheet - Page 442

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.20
442
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality
IDE_TIM — IDE Timing Register
(SATA–D31:F2)
Address Offset:
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
when the PCI functions are combined. These bits have no effect on SATA operation unless
otherwise noted.
13:12
11:10
Bit
9:8
15
14
7
6
5
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
0 = Disable
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes. See
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI
clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Drive 1 DMA Timing Enable (DTE1) — R/W.
0 = Disable
1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
Drive 1 Prefetch/Posting Enable (PPE1) — R/W.
0 = Disable
1 = Enable Prefetch and posting to the IDE data port for this drive.
Drive 1 IORDY Sample Point Enable (IE1) — R/W.
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
port will run in compatible timing.
Section 6.16 for more on ATA modes of operation.
Primary:
Secondary: 42
0000h
®
ICH5 to decode the associated Command Blocks (1F0–1F7h for primary,
40
–
–
41h
43h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16 bits