MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 262

• Manufacturer Part Number: MC9S08SH4CTG
• Manufacturer: Freescale

Specifications of MC9S08SH4CTG

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 256Byte
• # I/os (max): 13
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 4KB
• Lead Free Status / RoHS Status: Compliant

Chapter 16 Timer/PWM Module (S08TPMV3)
16.6.2.2.3
For channels configured for PWM operation there are two possibilities. When the channel is configured
for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The flag is cleared by the two-step sequence
described
16.7
262
1. Write to TPMxCNTH:L registers
2. Read of TPMxCNTH:L registers
3. Read of TPMxCnVH:L registers
4. Write to TPMxCnVH:L registers
(TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7]
Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter
(TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared
in this case.
(TPMxCNTH:TPMxCNTL))
— In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
(TPMxCnVH:TPMxCnVL))
— In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
— Input Capture Mode
— Output Compare Mode
The Differences from TPM v2 to TPM v3
Section 16.6.2, “Description of Interrupt Operation.”
TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was
read before the BDM mode became active, then any read of TPMxCNTH:L registers during
BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the
frozen TPM counter value.
TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear
this read coherency mechanism.
TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read
before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM
mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in
the TPMxCnVH:L registers.
TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency
mechanism.
In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the
TPM v2 allows these writes.
PWM End-of-Duty-Cycle Events
(Section 16.4.2.1, “Input Capture
MC9S08SH8 MCU Series Data Sheet, Rev. 3
(Section 16.4.2.2, “Output Compare
(Section 16.3.5, “TPM Channel Value Registers
(Section 16.3.2, “TPM-Counter Registers
(Section 16.3.2, “TPM-Counter Registers
Mode)
Mode)
Freescale Semiconductor