82V2608BB IDT, Integrated Device Technology Inc, 82V2608BB Datasheet - Page 20

• Manufacturer Part Number: 82V2608BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2608BB

• Utopia Level: Level 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Pin Count: 208
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table-2 Data Rates of Different Modes
3.2.1.1 Mode0
uous 1.544 Mb/s serial stream. There is no concept of time slot in an
unchannelized link. Each eight bits are grouped into an octet with arbi-
trary alignment. The first bit received/transmitted is the most significant
bit of an octet while the last bit is the least significant bit. The 1.544 MHz
data stream clock is provided by the system.
clock or independent clock. If common clock is used, TSCCK and
RSCCK are used as Tx clock and Rx clock respectively, and TSCFS and
RSCFS are used as common frame pulse in Tx and Rx directions
respectively. If independent clock is used, TSCK[i] and RSCK[i] are used
as Tx clock and Rx clock respectively, and TSF[i] and RSF[i] are used as
the frame pulse in Tx and Rx directions respectively.
3.2.1.2 Mode1~Mode4
while the line interface timing clock is 2.048 MHz (E1 clock). Thus the
mapping between T1 frame and E1 frame is needed. Two mapping
modes can be used: G.802 mapping mode and spaced mapping mode.
IDT82V2608
INTERFACE
In this mode, the transmit and receive data are viewed as a contin-
The 1.544 MHz clock in Tx and Rx directions can be either common
In these four modes, the transmit/receive data rate is T1 channelized
Mode10
Mode11
Mode12
Mode13
Mode14
Mode15
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode6
Mode7
Mode8
Mode9
Mode
IMA Data Rate Per Channel (Maximum)
1.544 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
2.048 Mb/s
1.920 Mb/s
1.984 Mb/s
1.920 Mb/s
1.984 Mb/s
20
Each mapping mode can be further divided into two data modes: T1
ISDN mode and T1 normal mode. The mapping is done in a frame-by-
frame fashion and the unassigned time slots are set to zero.
or independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively, and TSCFS and RSCFS are
used as common frame pulse in Tx and Rx directions respectively. If
independent clock is used, TSCK[i] and RSCK[i] are used as Tx clock
and Rx clock respectively, and TSF[i] and RSF[i] are used as the frame
pulse in Tx and Rx directions respectively.
G.802 Mapping
how 24 (or 23, in signalling mode) T1 time slots and one framing bit
(totally 193/185 bits per T1/T1-ISDN frame) are mapped to 32 E1 time
slots (256 bits). This mapping is done by mapping the 24 (or 23 in T1-
ISDN mode) T1 time slots to TS1~TS15 and TS17~TS25 (or
TS17~TS24), and mapping the framing bit to bit 1 of TS26/TS25. TS0,
TS16, TS27/TS26 through TS31 are all unassigned and set to zero
(refer to Figure-5).
In these modes, the clock for Tx and Rx can be either common clock
This mode supports ITU-T Recommendation G.802, which describes
Interface Clock (Maximum)
Inverse Multiplexing for ATM
1.544 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
1.544 MHz
1.544 MHz
8.192 MHz
8.192 MHz
8.192 MHz
8.192 MHz
2.048 MHz
2.048 MHz
2.048 MHz
8.192 MHz
8.192 MHz
December 4, 2006