82V2608BB IDT, Integrated Device Technology Inc, 82V2608BB Datasheet - Page 23

• Manufacturer Part Number: 82V2608BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2608BB

• Utopia Level: Level 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Pin Count: 208
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Channelized Non-Multi-Rate E1
pulse for E1 bit stream exchange between the IDT82V2608 and the line
interface. The E1 time slot 0 is not used for data exchange while time
slot 16 may or may not be used for data exchange, depending on
Signalling or Non-Signalling mode.
Signalling and Non-Signalling
exchange between the IDT82V2608 and the line interface. In non-
signalling mode, only time slot 0 is not used for data exchange.
3.2.1.7 Mode14~Mode15
signalling and non-signalling concepts are defined in
Non-Signalling
clock and 8 kHz common frame pulse.
the 8.192 MHz clock in Tx and Rx directions respectively, and TSCFS
and RSCFS are used as common frame pulse in Tx and Rx directions
respectively. The TSCK[i], TSF[i], RSCK[i] and RSF[i] pins are not used
and should be connected to ground. The unused RSD pins should also
be connected to ground.
3.2.2
Mode, the other is Independent Clock Mode. The timing clock mode can
be individually configured for each link. In IMA mode, AddTxLink
IDT82V2608
INTERFACE
In this mode, the system provides 2.048 MHz clock and 8 kHz frame
In signalling mode, time slot 0 and time slot 16 are not used for data
The multi-rate concept is defined in
In these modes, only the TSCCK and RSCCK pins are used to input
The data pins used for multiplexing are shown in Table-3.
Two timing clock modes can be selected. One is Common Clock
LINE INTERFACE TIMING CLOCK MODES
on
page
23. The system provides 8.192 MHz common
Multi-rate
on
page
Signalling and
22, and the
23
command and AddRxLink command can be used to configure the clock
mode in the transmit and receive directions respectively. In UNI mode,
ConfigUNILink command can be used to configure the clock mode.
are used as Tx clock and Rx clock respectively, and TSCFS and RSCFS
are used as common frame pulse in Tx and Rx directions respectively.
RSCK[i] are used as Tx clock and Rx clock respectively, and TSF[i] and
RSF[i] are used as the frame pulse in Tx and Rx directions respectively.
i.e., some links can work in Common Clock Mode while other links can
work in Independent Clock Mode.
used in Independent Clock Mode.
3.2.3
external loopback mode and the other is internal loopback mode. The
two loopback modes can be selected by ConfigLoopMode command.
looped back to the transmit side and is transmitted out. When this func-
tion is enabled, all the links will be in external loopback mode. Data will
not be transmitted to the Utopia interface.
receive side. When this function is enabled, all the links will be in internal
loopback mode. Data will not be transmitted to the FE Utopia interface.
If a link is configured in Common Clock Mode, TSCCK and RSCCK
If a link is configured in Independent Clock Mode, TSCK[i] and
These two timing clock modes can be configured at the same time,
The line interface mode7~mode10 and mode14~mode15 cannot be
The line interface supports two line loopback functions, one is
In external loopback mode, all the data received at the line side is
In internal loopback mode, the data transmitted are also sent to the
LINE INTERFACE LOOPBACK FUNCTION
Inverse Multiplexing for ATM
December 4, 2006