EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 328

IC STRATIX FPGA 10K LE 780-FBGA

EP1S10F780I6N

Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S10F780I6N

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Enhanced PLLs
Figure 1–7. extclkena Signals
1–18
Stratix Device Handbook, Volume 2
COUNTER
OUTPUT
CLKENA
CLKOUT
Programmable Bandwidth
Enhanced PLLs provide advanced control of the PLL bandwidth using
the programmable characteristics of the PLL loop, including loop filter
and charge pump.
Background
The PLL bandwidth is the measure of the PLLs ability to track the input
clock and jitter. It is determined by the 3-dB frequency of the closed-loop
gain in the PLL or approximately the unity gain point for open loop PLL
response. As
the same frequency.
Figure 1–8
shows, these points correspond to approximately
Altera Corporation
July 2005

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