EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 516
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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SERDES Bypass DDR Differential Signaling
Figure 5–29.
5–44
Stratix Device Handbook, Volume 2
inclock
datain
×
2 Data Rate Receiver Channel with Deserialization Factor of 8
DDR IOE
DFF
DFF
PLL
SERDES Bypass DDR Differential Signaling Transmitter
Operation
The
output circuitry to transmit high-speed serial data. The DDR output
circuitry consists of a pair of shift registers and a multiplexer. The shift
registers capture the parallel data on the clock’s rising edge (generated by
the PLL), and a multiplexer transmits the data in sync with the clock.
Figure 5–30
the clock. In this example, the inclock signal is running at half the speed
of the data. However, other combinations are possible.
the DDR output and the other modules used in a
interface with the system logic.
×4
×1
×
2 differential signaling transmitter uses the Stratix device DDR
Latch
shows the DDR timing relation between the parallel data and
Register
Register
Shift
Shift
D0, D2, D4, D6
D1, D3, D5, D7
Register
×
2 transmitter design to
Figure 5–31
Altera Corporation
Stratix
Logic
Array
Clock
July 2005
shows
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