EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 576

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Operational Modes
6–26
Stratix Device Handbook, Volume 2
FIR Filters
The four-multiplier adder mode can be used for FIR filter and complex
FIR filter applications. The DSP block combines a four-multiplier adder
with the input registers configured as shift registers. One set of shift
inputs contains the filter data, while the other holds the coefficients,
which can be loaded serially or in parallel (see
The input shift register eliminates the need for shift registers external to
the DSP block (e.g., implemented in device logic elements). This
architecture simplifies filter design and improves performance because
the DSP block implements all of the filter circuitry.
1
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, you can cascade DSP blocks
with additional adder stages implemented in logic elements.
Serial shift inputs in 36-bit simple multiplier mode require
external registers.
Figure
6–15).
Altera Corporation
July 2005