EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 353

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
FPll7clk
FPll8clk
FPll9clk
FPll10clk
Clock Feedback Input Pins
Pll5_fbp/n
Pll6_fbp/n
Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 2 of 2)
Clock Input
This is a fast PLL. The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other
PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
This is an enhanced PLL.
The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Pins
Table
1–14:
PLL 1
(1)
PLL 2
(1)
Clock Output Connections
Enhanced PLLs have outputs for two regional clock outputs and four
global outputs. There is line sharing between clock pins, global and
regional clock networks and all PLL outputs. Check
and
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions. Enhanced PLLs 5 and 6 drive out to single-
ended pins as shown in
ended pins.
You can connect each fast PLL 1, 2, 3, or 4 outputs (g0, l0, and l1) to either
a global or a regional clock. (PLLs 3 and 4 are not available on Stratix GX
devices.) There is line sharing between clock pins,
and regional clock networks and all PLL outputs. Check
1–22
automatically maps to regional and global clocks to avoid any
restrictions.
All Stratix Devices
PLL 3
(1)
Figures 1–21
to make sure that the clocking is valid. The Quartus II software
PLL 4
(1)
PLL 5
and
(2)
v
General-Purpose PLLs in Stratix & Stratix GX Devices
1–22
PLL 6
Table
(2)
v
to make sure that the clocking scheme is valid.
1–15. PLLs 11 and 12 drive out to single-
PLL 7
EP1S30, EP1S40, EP1S60 &
(1)
v
EP1S80 Devices Only
PLL 8
Stratix Device Handbook, Volume 2
(1)
v
PLL 9
(1)
v
FPLLCLK
Tables 1–15
10
PLL
v
(1)
Figures 1–21
pins, global
11
Devices Only
EP1S40 (3),
PLL
EP1S60 &
EP1S80
(2)
and
12
PLL
1–16
1–43
and
(2)