EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 735

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 11–7. Configuring with a Combined PS & Configuration Device Scheme
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Altera Corporation
July 2005
You should connect the pull-up resistor to the same supply voltage as the configuration device.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
Pin 6 of the header is a V
device’s V
You should not attempt configuration with a download cable while a configuration device is connected to a Stratix
or Stratix GX device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device. Remove the download cable when configuring with a configuration device.
If nINIT_CONF is not used, nCONFIG must be pulled to V
If external pull-ups are used on CONF_DONE and nSTATUS pins, they should always be 10 k
the internal pull-ups of the configuration device only if the CONF_DONE and nSTATUS signals are pulled-up to 3.3 V
or 2.5 V (not 1.8 V or 1.5 V).
Figure
10 kΩ
V
CCIO
CC
10 kΩ
11–7:
(4)
(1)
f
. This is a no-connect pin for the ByteBlasterMV header.
V
CC
(4)
GND
(2)
(1)
V
CC
IO
Stratix or Stratix GX Device
reference voltage for the MasterBlaster output driver. V
For more information on how to use the MasterBlaster or ByteBlasterMV
cables, see the following documents:
■
■
■
■
DATA0
nCONFIG
MSEL0
MSEL1
MSEL2
nCE
USB-Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
CONF_DONE
nSTATUS
DCLK
nCEO
10 kΩ
N.C.
(6)
V
CC
(4)
CC
(1)
V
either directly or through a resistor.
CC
(4)
10 kΩ
(1)
(6)
Configuring Stratix & Stratix GX Devices
(2)
V
CC
Stratix Device Handbook, Volume 2
10 kΩ
(4)
(1)
10-Pin Male Header
Pin 1
Download Cable
IO
(PS Mode)
DCLK
DATA
OE
nCS
nINIT_CONF (5)
should match the target
Configuration
(6)
GND
Device
(6)
V
resistors. You can use
CC
VIO (3)
GND
11–17