EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 467
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 467 of 864
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Altera Corporation
June 2006
Device & Pin Options
Click Device & Pin Options in the Compiler Settings dialog box to
access the I/O pin settings. For example, in the Voltage tab you can select
a default I/O standard for all pins for the targeted device. I/O pins that
do not have a specific I/O standard assignment default this standard.
Click OK when you are done setting I/O pin options to return to the
Compiler Settings dialog box.
Assign Pins
Click Assign Pins in the Compiler Settings dialog box to view the
device’s pin settings and pin assignments (see
the pin settings under Available Pins & Existing Assignments. The
listing does not include V
information for each pin includes:
■
■
■
■
■
■
■
■
Figure 4–23. Assign Pins
Number
Name
I/O Bank
I/O Standard
Type (e.g., row or column I/O and differential or control)
SignalProbe Source Name
Enabled (that is, whether SignalProbe routing is enabled or disabled
Status
Selectable I/O Standards in Stratix & Stratix GX Devices
REF
pins because they are dedicated pins. The
Stratix Device Handbook, Volume 2
Figure
4–23). You can view
4–39
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