EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 404

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

External Memory Standards
Figure 3–5. Data & Clock Relationship During a QDRII SRAM Read
Notes to
(1)
(2)
(3)
(4)
(5)
3–8
Stratix Device Handbook, Volume 2
Cn/Kn
CQn
CQ
C/K
Q
The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18.
CO is the data clock-to-out time and t
t
t
t
CLZ
CQD
CQQO
Figure
and t
is the skew between CQn and data edges.
and t
CHZ
CQOH
3–5:
are bus turn-on and turn-off times respectively.
f
are skew between the C or Cn (or K or Kn in single-clock mode) and the CQ or CQn clocks.
clock mode, or K or Kn in single clock mode. The edge-aligned CQ and
CQn clocks accompany the read data for data capture in Stratix and
Stratix GX devices.
When writing to QDRII SRAM devices, data is generated by the write
clock, while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
Go to www.qdrsram.com for the QDR SRAM and QDRII SRAM
specifications. For more information on QDR and QDRII SRAM
interfaces in Stratix and Stratix GX devices, see AN 349: QDR SRAM
Controller Reference Design for Stratix & Stratix GX Devices.
ZBT SRAM
ZBT SRAM eliminate dead bus cycles when turning a bidirectional bus
around between reads and writes or between writes and reads. ZBT
allows for 100% bus utilization because ZBT SRAM can be read or written
on every clock cycle. Bus contention can occur when shifting from a write
cycle to a read cycle or vice versa with no idle cycles in between.
ZBT SRAM allows small amounts of bus contention. To avoid bus
contention, the output clock-to-low-impedance time (t
t
t
CCQO (5)
CLZ (3)
DOH
t
CO (2)
is the data output hold time between burst.
QA
t
QA + 1
DOH (2)
t
CQD (4)
t
t
CQOH (5)
CO (2)
Note (1)
QA + 2
QA + 3
t
t
CQD (4)
CHZ (3)
ZX
Altera Corporation
) must be greater
June 2006