EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 698

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

TriMatrix Memory
10–14
Stratix Device Handbook, Volume 2
f
If the functionality of the APEX II or APEX 20K memory megafunction
differs from the altsyncram functionality and at least one clock feeds
the memory megafunction, the Quartus II software converts the APEX II
or APEX 20K memory megafunction to the Stratix or Stratix GX
altsyncram megafunction. This conversion is useful for an initial
evaluation of how a design might perform in Stratix or Stratix GX devices
and should only be used for evaluation purposes. During this process, the
Quartus II software generates a warning that the conversion may be
functionally incorrect and timing results may not be accurate. Since the
functionality may be incorrect and the compilation is only intended for
comparative purposes, the Quartus II software does not generate a
programming file. A functionally correct conversion requires manually
instantiating the altsyncram megafunction and may require additional
design changes.
If the previous memory function does not have a clock (fully
asynchronous), the fitting-evaluation conversion results in an error
message during compilation and does not successfully convert the
design.
See AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix & Stratix GX Designs for more information.
Table 10–5
migration mode and the resulting behavior of the Quartus II software.
The most common cases where design-migration mode may have
difficulty converting the existing design are when:
■
A port is reading from an address that is being written to by another
port (mixed-port read-during-write mode). If both ports are using
the same clock, the read port in Stratix and Stratix GX devices do not
see the new data until the next clock cycle, after the new data was
written.
summarizes the possible scenarios when using design
Altera Corporation
July 2005