EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 481

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 5–5. Stratix High-Speed Interface Serialized in
Altera Corporation
July 2005
Logic Array
Stratix
Stratix Differential I/O Transmitter Operation
You can configure any of the Stratix differential output channels as a
transmitter channel. The differential transmitter is used to serialize
outbound parallel data.
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 5–5
channel and
and clocks in Stratix devices in
multiplier and J is the data parallelization division factor.
Transmitter Circuit
shows the block diagram of a single SERDES transmitter
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD0
PD1
Figure 5–6
Fast
PLL
Register
Parallel
High-Speed Differential I/O Interfaces in Stratix Devices
× W
TXLOADEN
×
shows the timing relationship between the data
10 Mode
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
×
10 mode. W is the low-frequency
Register
Serial
Stratix Device Handbook, Volume 2
TXOUT+
TXOUT−
5–9