EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 563

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Altera Corporation
July 2005
Because the DSP block outputs communicate horizontally, and because
each DSP block row has more outputs than an LAB (18 from the DSP
block compared to 10 from an LAB), the DSP block has double the
number of row channel drivers compared to an LAB. The DSP block has
the same number of row channels, but the row channels are staggered as
if there were two LABs within each block. The DSP blocks have the same
number of column channels as LABs because DSP blocks communicate
primarily through row channels.
Row Interface Block
Each row interface block connects to the DSP block row structure with
21 signals. Because each DSP block has eight row interface blocks, this
block receives 162 signals from the eight row interfaces. Of the
162 signals, 144 are data inputs and 18 are control signals.
page 6–14
shows one row block within the DSP block.
DSP Blocks in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
Figure 6–7 on
6–13

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