EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 519

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 5–34. HyperTransport & LVPECL Differential Termination
Altera Corporation
July 2005
Transmitter
Differential
Figure 5–33. LVDS Differential On-Chip Termination
HyperTransport & LVPECL Differential Termination
HyperTransport and LVPECL I/O standards are terminated by an
external 100- resistor on the input pin.
with differential termination for the HyperTransport or LVPECL I/O
standard.
PCML Differential Termination
The PCML I/O technology is an alternative to the LVDS I/O technology,
and use an external voltage source (V
input side and a pair of 50- resistors on the output side.
shows the device with differential termination for PCML I/O standard.
LVDS Transmitter
Z
Z
0
0
= 50 Ω
= 50 Ω
High-Speed Differential I/O Interfaces in Stratix Devices
R
D
Z
Z
0
0
= 50 Ω
= 50 Ω
Differential Receiver
TT
Stratix Device Handbook, Volume 2
), a pair of 100- resistors on the
Figure 5–34
On-Chip 100-Ω Termination
R
LVDS Receiver with
D
shows the device
Figure 5–35
5–47