EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 578

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Software Support
Software
Support
Conclusion
6–28
Stratix Device Handbook, Volume 2
f
f
f
Altera provides two distinct methods for implementing various modes of
the DSP block in your design: instantiation and inference. Both methods
use the following three Quartus II megafunctions:
■
■
■
You can instantiate the megafunctions in the Quartus II software to use
the DSP block. Alternatively, with inference, you can create a HDL design
an synthesize it using a third-party synthesis tool like LeonardoSpectrum
or Synplify or Quartus II Native Synthesis that infers the appropriate
megafunction by recognizing multipliers, multiplier adders, and
multiplier accumulators. Using either method, the Quartus II software
maps the functionality to the DSP blocks during compilation.
See the Implementing High-Performance DSP Functions in Stratix & Stratix
GX Devices chapter in the Stratix Device Handbook, Volume 2 or the
Stratix GX Device Handbook, Volume 2 for more information on using DSP
blocks to implement high-performance DSP functions such as FIR filters,
IIR filters, and discreet cosine transforms (DCTs).
See Quartus II On-Line Help for instructions on using the megafunctions
and the MegaWizard Plug-In Manager.
For more information on DSP block inference support, see the
Recommended HDL Coding Styles chapter of the Quartus II Development
Software Handbook v4.1, Volume 1.
The Stratix and Stratix GX device DSP blocks are optimized to support
DSP applications that need high data throughput, such as FIR filters, FFT
functions, and encoders. These DSP blocks are flexible and can be
configured in one of four operational modes to suit any application need.
The DSP block’s adder/subtractor/accumulator and the summation
blocks minimize the amount of logic resources used and provide efficient
routing. This efficiency results in improved performance and data
throughput for DSP applications. The Quartus II software, together with
the LeonardoSpectrum and Synplify software, provides a complete and
easy-to-use flow for implementing functionality in the DSP block.
lpm_mult
altmult_add
altmult_accum
Altera Corporation
July 2005