ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 17

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Power Settings
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. In the sleep mode, assertion of a wakeup event
enabled in the SIC_IWRx register causes the processor to sense
the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
In the sleep mode, system DMA access to L1 memory is not
supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
Full On
Active
Sleep
Deep Sleep
Hibernate
Enabled
Enabled/
Disabled
Enabled
Disabled
Disabled
1.25V
R1
330
C1
0.047 F
2% PPS
600Z
0.01 F
1%
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
No
Yes
-
-
-
C2
330pF
2% PPS
24.576MHz
0.1 F
Enabled
Enabled
Disabled
Disabled
Disabled
VDDINT
GND
VDDMP
GNDMP
MXO
MXI
MLF_P
MLF_M
ADSP-BF549
Enabled
Enabled
Enabled
Disabled
Disabled
Rev. C | Page 17 of 100 | February 2010
PG11/MTXON
PC7/RSCLK0
PC3/TSCLK0
PH7/MRXON
PC1/MMCLK
PC5/MBCLK
PC2/DT0PRI
PC4/RFS0
Figure 5. MXVR MOST Connection
PH6/MRX
PH5/MTX
On
On
On
On
Off
MFS
10k
33
33
33
27
5.0V
XN4114
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This
powered-down mode can only be exited by assertion of the reset
interrupt (RESET) or by an asynchronous interrupt generated
by the RTC. In deep sleep mode, an asynchronous RTC inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by using the
bfrom_SysControl() function in the on-chip ROM. This sets the
internal power supply voltage (V
greatest power savings mode. Any critical information stored
internally (memory contents, register contents, and so on) must
be written to a non-volatile storage device prior to removing
power if the processor state is to be preserved.
Since V
pins three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, by the USB,
and by some GPIO pins. It can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin. Waking up
from hibernate state initiates the hardware reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or DDR
memory.
600Z
600Z
DDEXT
0
is still supplied in this mode, all of the external
RXVCC
RXGND
TXVCC
TXGND
TX_DATA
RX_DATA
STATUS
L/RCLK
MCLK
BCLK
SDATA
AUDIO DAC
MOST FOT
DDINT
MOST
NETWORK
AUDIO
CHANNELS
) to 0 V to provide the