ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 49

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR SDRAM/Mobile DDR SDRAM Timing
Table 33
SDRAM/mobile DDR SDRAM read cycle timing.
Table 33. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
For 7.50 ns ≤ t
For t
AC
DQSCK
DQSQ
QH
RPRE
RPST
CK
≥ 10 ns.
and
CK
Figure 18/Figure 19
< 10 ns.
Access Window of DQ0-15 to DCK0-1
Access Window of DQS0-1 to DCK0-1
DQS0-1 to DQ0-15 Skew, DQS0-1 to Last
DQ0-15 Valid
DQ0-15 to DQS0-1 Hold, DQS0-1 to First
DQ0-15 to Go Invalid
DQS0-1 Read Preamble
DQS0-1 Read Postamble
DCK0-1
DQS0-1
DCK0-1
DQS0-1
DQ0-15
DQ0-15
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
describe DDR
t
t
RPRE
RPRE
t
t
DQSQ
DQSQ
Figure 19. Mobile DDR SDRAM Controller Read Cycle Timing
t
DQSCK
Figure 18. DDR SDRAM Controller Read Cycle Timing
t
t
DQSCK
AC
t
AC
Rev. C | Page 49 of 100 | February 2010
t
t
QH
QH
Dn
Dn
DDR SDRAM
Min
–1.25
–1.25
t
t
0.9
0.4
CK
CK
Dn+1
/2 – 1.25
/2 – 1.75
Dn+1
1
2
Dn+2
Dn+2
Max
+1.25
+1.25
0.90
1.1
0.6
t
RPST
Dn+3
t
Dn+3
RPST
Mobile DDR SDRAM
Min
0.0
0.0
t
0.9
0.4
CK
/2 – 1.25
Max
6.00
6.00
0.85
1.1
0.6
Unit
ns
ns
ns
ns
t
t
CK
CK