ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 72

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOSTDP A/C Timing-Host Read Cycle
Table 54
cycle timing requirements.
Table 54. Host Read Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
NM (Not Measured) — This parameter is based on t
SADRDL
HADRDH
RDWL
RDWL
RDWH
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
DDARWH
ACC
HDARWH
DMA FIFO status. This is system design dependent.
and
HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge
HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge
HOST_RD Pulse Width Low (ACK Mode)
HOST_RD Pulse Width Low (INT Mode)
HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and
HOST_WR Falling Edge
HOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0
HOST_D15–0 Valid Prior HOST_ACK Rising Edge (ACK Mode)
HOST_ACK Falling Edge After HOST_CE (ACK Mode)
HOST_ACK Low Pulse-Width for Read Access (ACK Mode)
HOST_D15–0 Disable After HOST_RD
HOST_D15–0 Valid After HOST_RD Falling Edge (INT Mode)
HOST_D15–0 Hold After HOST_RD Rising Edge
Figure 45
describe the HOSTDP A/C host read
HOST_ADDR
HOST_DATA
HOST_ACK
HOST_RD
HOST_CE
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host
In
t
DRDYRDL
t
Rev. C | Page 72 of 100 | February 2010
Figure
SADRDL
Figure 45. HOSTDP A/C—Host Read Cycle
45, HOST_DATA is HOST_D0–D15.
t
SDATRDY
t
ACC
t
t
RDYPRD
RDWL
t
HDARWH
Min
4
2.5
t
1.5 × t
2 × t
t
1.0
t
DRDYRDL
SCLK
DRDHRDY
t
DDARWH
SCLK
– 4.0
t
HADRDH
t
SCLK
RDWH
+ t
+ 8.7
RDYPRD
+ t
DRDHRDY
Max
11.25
NM
8.0
1.5 × t
1
SCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns