ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 73

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HOSTDP A/C Timing-Host Write Cycle
Table 55
cycle timing requirements.
Table 55. Host Write Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
NM (not measured)—This parameter is based on t
SADWRL
HADWRH
WRWL
WRWH
DWRHRDY
HDATWH
SDATWH
DRDYWRL
RDYPWR
FIFO status. This is system design dependent.
and
HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge
HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge
HOST_WR Pulse Width Low (ACK Mode)
HOST_WR Pulse Width Low (INT Mode)
HOST_WR Pulse Width High or Time Between HOST_WR Rising Edge
and HOST_RD Falling Edge
HOST_WR Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0
HOST_D15–0 Hold After HOST_WR Rising Edge
HOST_D15–0 Setup Before HOST_WR Rising Edge
HOST_ACK Falling Edge After HOST_CE Asserted (ACK Mode)
HOST_ACK Low Pulse-Width for Write Access (ACK Mode)
Figure 46
describe the HOSTDP A/C host write
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOST_ADDR
HOST_DATA
HOST_ACK
HOST_WR
HOST_CE
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host DMA
t
In
t
DRDYWRL
SADWRL
Figure
Rev. C | Page 73 of 100 | February 2010
Figure 46. HOSTDP A/C- Host Write Cycle
46, HOST_DATA is HOST_D0–D15.
t
SDATWH
t
RDYPWR
t
WRWL
t
DWRHRDY
t
HDATWH
Min
4
2.5
t
1.5 × t
2 × t
2.5
3.5
DRDYWRL
t
HADWRH
t
WRWH
SCLK
SCLK
+ t
+ 8.7
RDYPRD
+ t
DWRHRDY
Max
NM
11.25
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns