ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 19

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in
ation is discussed in detail in an Application Note, Using Third
Overtone Crystals (EE-168).
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable 0.5× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 8×, but it can
be modified by a software instruction sequence. This sequence
is managed by the bfrom_SysControl() function in the on-chip
ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
Whereas the maximum allowed CCLK and SCLK rates depend
on the applied voltages V
permitted to run up to the frequency specified by the part’s
speed grade.
The CLKOUT pin reflects the SCLK frequency to the off-chip
world. It functions as a reference for many timing specifications.
While inactive by default, it can be enabled using the
EBIU_AMGCTL register.
Note: For CCLK and SCLK specifications, see
CLKOUT
CLKBUF
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
CLKIN
Figure
REQUIRES PLL SEQUENCING
Figure 8. Frequency Modification Methods
DYNAMIC MODIFICATION
Figure 7. External Crystal Connections
CLKIN
EN
EN
7. A design procedure for third-overtone oper-
0.5x - 64x
PLL
BLACKFIN
18 pF*
Figure 8 on Page
DDINT
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TO PLL CIRCUITRY
XTAL
and V
VCO
18 pF*
700 0
0
DDEXT
*
DYNAMIC MODIFICATION
, the VCO is always
19, the core clock
1, 2, 4, 8
1:15
Table
ON-THE-FLY
F R OVERTONE
OPERA
O
V DDEXT
1M
Rev. C | Page 19 of 100 | February 2010
TION ONLY
16.
CCLK
SCLK
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
ratio is 4.
Table 7. Example System Clock Ratios
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
capability is useful for fast core frequency modifications.
The maximum CCLK frequency not only depends on the part’s
speed grade, it also depends on the applied V
Table 13 on Page 35
Table 8. Core Clock Ratios
BOOTING MODES
The ADSP-BF54x Blackfin processors have many mechanisms
(listed in
nal memory after a reset. The boot mode is specified by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: master and slave. In master boot
Signal Name
SSEL3–0
0010
0110
1010
Signal Name
CSEL1–0
00
01
10
11
Table 7
8. The default ratio is 1. This programmable core clock
Table
illustrates typical system clock ratios. The default
9) for automatically loading internal and exter-
Divider Ratio
VCO/SCLK
2:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
for details.
500
Example Frequency Ratios
(MHz)
VCO
300
300
500
200
Example Frequency Ratios
(MHz)
VCO
200
300
SCLK
. The SSEL value can be
DDINT
SCLK
100
50
50
CCLK
300
150
125
25
voltage. See