FW80960VH100 Intel, FW80960VH100 Datasheet - Page 11

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

2.2.1
2.2.2
2.2.3
2.2.4
Preliminary Datasheet
A 32-bit high-performance bus controller interfaces the 80960VH to external memory and
peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate
of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960VH’s bus controller to match an application’s fundamental memory
organization. Physical bus width is programmable for up to eight regions. Data caching is
programmed through a group of logical memory templates and a defaults register. The Bus Control
Unit’s features include:
Upon reset, the 80960VH conducts an internal self test. Before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
Initialization Boot Record.
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the Timer Unit registers.
These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-
shot mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960VH’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected.
Priority Interrupt Controller
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960VH exploits several techniques to minimize latency:
Faults and Debugging
The 80960VH employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
Burst Bus
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Multiplexed external bus minimizes pin count
32-, 16- and 8-bit bus widths simplify I/O interfaces
External ready control for address-to-data, data-to-data and data-to-next-address wait state
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Little endian byte ordering
Unaligned bus accesses performed transparently
Three-deep load/store queue decouples the bus from the 80960 core
Interrupt vectors and interrupt handler routines can be reserved on-chip
Register frames for high-priority interrupt handlers can be cached on-chip
The interrupt stack can be placed in cacheable memory space
80960VH
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