FW80960VH100 Intel, FW80960VH100 Datasheet - Page 24

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
24
Table 8.
Table 9.
Memory Controller Signal Descriptions (Sheet 2 of 2)
DMA, I
MA11:0
MWE3:0#
RAS3:0#
DACK#
DREQ#
SCL
SDA
WAIT#
NAME
2
NAME
C Units Signal Descriptions
TYPE
R(H)
H(Q)
P(Q)
H(Q)
P(Q)
H(Q)
P(Q)
H(Q)
P(Q)
R(Z)
R(Z)
R(1)
S(L)
OD
OD
I/O
I/O
O
O
I
TYPE
H(Q)
H(Q)
H(Q)
R(X)
P(Q)
P(Q)
P(Q)
R(1)
R(1)
O
O
O
DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this
signal to indicate (1) it can receive new data from an external device or (2) it
has data to send to an external device. This signal has a weak internal pullup
which is active during reset to ensure normal operation.
DMA DEMAND MODE REQUEST External devices use this signal to
indicate (1) new data is ready for transfer to the DMA controller or (2) buffers
are available to receive data from the DMA controller.
I
I
WAIT is an output that allows the DMA controller to insert wait states during
DMA accesses to an external memory system.
2
2
C CLOCK provides synchronous I
C DATA used for data transfer and arbitration on the I
MULTIPLEXED ADDRESS signals are multi-purpose depending on the
device that is selected.
For memory banks 0 and 1, these signals output address bits A13:2.
These address bits are incremented for each data transfer of a burst
access.
For DRAM bank, these signals output the row/column multiplexed
address bits 11:0. The relationship between the AD31:0 lines and the
MA11:0 lines depends on the bank size, type and arrangement of the
DRAM that is accessed.
MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH
devices. The MWE’s rising edge strobes valid data into these devices.
MWE0# is asserted for writes to the BE0# lane
MWE1# is asserted for writes to the BE1# lane
MWE2# is asserted for writes to the BE2# lane
MWE3# is asserted for writes to the BE3# lane
ROW ADDRESS STROBE signals are used for DRAM accesses and
are asserted when the MA11:0 signals contain a valid row address.
RAS3:0# always deasserts after the last data transfer in a DRAM
access.
Non-Interleaved Operation:
Interleaved Operation:
RAS0# = Bank0 access
RAS1# = Bank1 access
RAS2# = Bank2 access
RAS3# = Bank3 access
RAS0,2# = Even leaf
RAS1,3# = Odd leaf
DESCRIPTION
DESCRIPTION
2
C bus operation.
Preliminary Datasheet
2
C bus.