FW80960VH100 Intel, FW80960VH100 Datasheet - Page 22

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
22
Table 7.
PCI Signal Descriptions (Sheet 2 of 2)
P_LOCK#
P_PAR
P_PERR#
P_REQ#
P_RST#
P_SERR#
P_STOP#
P_TRDY#
NOTE:
1.
PCI signal functions are summarized in this data sheet; refer to the
a more complete definition.
NAME
TYPE
K(Q)
K(Q)
S(L)
R(Z)
R(Z)
R(Z)
A(L)
R(Z)
R(Z)
R(Z)
OD
I/O
I/O
I/O
I/O
I/O
O
I
I
PRIMARY PCI BUS LOCK indicates an atomic operation that may require
multiple transactions to complete.
PRIMARY PCI BUS PARITY. This signal ensures even parity across
P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.
PRIMARY PCI BUS PARITY ERROR is used for reporting data parity errors
during all PCI transactions except a special cycle.
PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent desires
use of the bus. This is a point to point signal.
PRIMARY RESET brings 80960VH to a consistent state. When P_RST# is
asserted:
P_RST# may be asynchronous to P_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
PRIMARY PCI BUS SYSTEM ERROR reports address and data parity errors
on the special cycle command, or any other system error where the result
would be catastrophic.
PRIMARY PCI BUS STOP indicates that the current target is requesting the
master to stop the current transaction on the primary PCI bus.
PRIMARY PCI BUS TARGET READY indicates the target agent's (selected
device's) ability to complete the current data phase of the transaction.
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as P_SERR# are floated.
• S_RST# asserts.
DESCRIPTION
PCI Local Bus Specification , revision 2.2
1
Preliminary Datasheet
for