FW80960VH100 Intel, FW80960VH100 Datasheet - Page 9

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
Preliminary Datasheet
Key Functional Units
DMA Controller
The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents
and 80960 local memory. Two separate DMA channels accommodate data transfers for the primary
PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable
only through the i960 core processor.
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960VH local
memory. The 80960VH has direct access to the PCI bus. The ATU supports transactions between
PCI address space and 80960VH address space.
Address translation is controlled through programmable registers accessible from the PCI interface
and the 80960 core. Dual access to registers allows flexibility in mapping the two address spaces.
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the 80960VH. It
uses interrupts to notify each system when new data arrives. The MU has two messaging
mechanisms. Each allows a host processor or external PCI device and the 80960VH to
communicate through message passing and interrupt generation. The two mechanisms are Message
Registers and Doorbell Registers.
Memory Controller
The Memory Controller allows direct control of external memory systems, including DRAM,
SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically
does not require external logic. It features programmable chip selects, a wait state generator and
byte parity. External memory can be configured as PCI addressable memory.
Core and Peripheral Unit
The Core and Peripheral Unit allows software to control the 80960VH through the primary PCI
bus. For example, the 80960 processor core and the 80960VH local bus can be reset via the PCI
bus.
I
The I
slave device residing on the I
Semiconductor consisting of a two pin interface. The bus allows the 80960VH to interface to other
I
hardware for an economical system to relay status and reliability information on the I/O subsystem
to an external device. For more information, see I
Semiconductor).
2
2
C peripherals and microcontrollers for system management functions. It requires a minimum of
C Bus Interface Unit
2
C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and
2
C bus. The I
2
C bus is a serial bus developed by Philips
2
C Peripherals for Microcontrollers (Philips
80960VH
9