FW80960VH100 Intel, FW80960VH100 Datasheet - Page 20

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
20
Table 5.
Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)
TDO
TMS
TRST#
LCDINIT#
V
V
V
N.C.
VCCPLL2:1
CC
CC5
SS
REF
NAME
TYPE
R(Q)
H(Q)
P(Q)
S(L)
A(L)
O
–
–
–
–
I
I
I
I
TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on
the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the
Test Access Port. At other times, TDO floats.
TEST MODE SELECT is sampled at the rising edge of TCK to select the
operation of the test logic for IEEE 1149.1 Boundary Scan testing. This
signal has a weak internal pullup to ensure normal operation.
TEST RESET asynchronously resets the Test Access Port (TAP) controller
function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the
Boundary Scan feature, connect a pulldown resistor (1.5 K ) between this
signal and V
V
which must be overcome during reset to ensure normal operation.
NOTE: The system must ensure that TRST# is asserted after power-up to
LCD INITIALIZATION is a static signal used to initialize the internal logic of
the LCD960 debugger. This signal has an internal pullup for normal
operation.
POWER. Connect to a 3.3 Volt power board plane.
5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the
5 V-tolerant I/O buffers. Connect this signal to +5 V for use with signals
which exceed 3.3 V. When all inputs are from 3.3 V components, connect
this signal to 3.3 V.
GROUND. Connect to a V
NO CONNECT. Do not make electrical connections to these balls.
PLL POWER. For external connection to a 3.3 V V
to PLLs requires external filtering. See Section 4.2, VCCPLL Pin
Requirements.
SS
; however, no resistor is required. The signal has a weak internal pullup
put the TAP controller in a known state. Failure to do so may
cause improper processor operation.
SS
. When TAP is not used, this signal must be connected to
SS
board plane.
DESCRIPTION
Preliminary Datasheet
CC
board plane. Power