FW80960VH100 Intel, FW80960VH100 Datasheet - Page 18

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
18
Table 4.
Signal Descriptions (Sheet 3 of 4)
LOCK#/ONCE#
LRDYRCV#/
STEST
HOLD
HOLDA
RDYRCV#
NAME
TYPE
R(H)
P(Q)
R(H)
H(Q)
P(Q)
P(Q)
S(L)
H(Z)
S(L)
R(0)
H(1)
S(L)
I/O
I/O
O
I
I
BUS LOCK indicates that an atomic read-modify-write operation is in
progress. The LOCK# output is asserted in the first clock of an atomic
operation and deasserted in the last data transfer of the sequence. The
processor does not grant HOLDA while asserting LOCK#. This prevents
external agents from accessing memory involved in semaphore operations.
0 = Atomic Read-Modify-Write in Progress
1 = No Atomic Read-Modify-Write in Progress
ONCE MODE: The processor samples the ONCE input during reset. When
ONCE# is asserted LOW at the end of reset, the processor enters ONCE
mode, stops all clocks and floats all output signals. This signal has a weak
internal pullup which is active during reset to ensure normal operation when
the signal is not connected.
0 = ONCE Mode Enabled
1 = ONCE Mode Not Enabled
LOCAL READY/RECOVER, generated by the 80960VH’s memory controller
unit, is an output version of the READY/RECOVER (RDYRCV#) signal. Refer
to the RDYRCV# signal description.
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of P_RST#. When STEST is
asserted, the processor performs its internal self-test and the external bus
confidence test. When STEST is deasserted, the processor performs only the
external bus confidence test. This signal has a weak internal pullup which is
active during reset to ensure normal operation.
0 = Self Test Disabled
1 = Self Test Enabled
HOLD is a request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T
When HOLD is deasserted, the processor deasserts HOLDA and enters
either the T
lines. See
0 = No Hold Request
1 = Hold Requested
HOLD ACKNOWLEDGE indicates to an external bus master that the
processor has relinquished bus control. The processor can grant HOLD
requests and enter the T
operation. See
0 = No Hold Acknowledged
1 = Hold Acknowledged
READY/RECOVER is only used in systems that use an external memory
controller (and do not use the 80960VH’s memory controller unit). This signal
indicates that data on AD lines can be sampled or removed. When RDYRCV#
is not asserted during a T
inserting a wait state (T
0 = Sample Data
1 = Do Not Sample Data
RDYRCV# has an alternate function during the recovery (T
processor continues to insert recovery states until it samples the signal HIGH.
This gives slow external devices more time to float their buffers before the
processor drives addresses.
0 = Insert Wait States
1 = Recovery Complete
When using the internal memory controller, connect this signal to V
a 2.7 K
resistor.
Figure , (pg.
i
or
T
Figure , (pg.
a
state, resuming control of the address/data and control
w
61).
h
).
d
state and while halted as well as during regular
cycle, the T
61).
DESCRIPTION
d
cycle extends to the next cycle by
Preliminary Datasheet
r
) state. The
CC
h
state.
through