DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 10

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
3.2 PCI Bus Interface
The DP83820 implements the Peripheral Component
Interconnect (PCI) bus interface as defined in PCI Local
Bus Specification Version 2.2. When internal register are
being accessed the DP83820 acts as a PCI target (slave).
When accessing host memory for descriptor or packet data
transfer, the DP83820 acts as a PCI bus master.
All required pins and functions are implemented. The
optional interface pin INTA for support of interrupt requests
is implemented as well. The bus interface also supports 64-
bit and 66Mhz operation in addition to the more common
32-bit and 33-Mhz capabilities.
For more information, refer to the PCI Local Bus
Specification version 2.2, December 18, 1998.
When configured for big-endian mode (CFG:BEM=1), the
byte orientation for receive and transmit data and
descriptors in system memory is as follows:
3.2.2 Interrupt Control
Interrupts are performed by asynchronously asserting the
INTAN pin. This pin is an open drain output. The source of
the interrupt can be determined by reading the Interrupt
Status Register (ISR) (See Section 4.2.6). One or more
bits in the ISR will be set, denoting all currently pending
interrupts. Reading of the ISR clears ALL bits. Masking of
specific interrupts can be accomplished by using the
Interrupt Mask Register (IMR) (See Section 4.2.7).
Assertion of INTAN can be prevented by clearing the
Interrupt Enable bit in the Interrupt Enable Register (See
Section 4.2.8). This allows the system to defer interrupt
processing as needed.
3.2.3 Latency Timer
The Latency Timer described in CFGLAT:LAT (See Section
4.1.4) defines the maximum number of bus clocks that the
device will hold the bus. Once the device gains control of
the bus and issues FRAMEN, the Latency Timer will begin
counting down. If GNTN is deasserted before the DP83820
has finished with the bus, the device will maintain
ownership of the bus until the timer reaches zero (or has
finished the bus transfer). The timer is an 8-bit counter, with
the lower 4 bits hard-coded to 1111b. This means that the
timer value can only be incremented in units of 16 clocks.
3.2.4 64-Bit Data Operation
The DP83820 supports 64-bit operation as a bus master
for transferring descriptor and packet data information. This
mode can be enabled or disabled through configuration
from EEPROM. As a target, the DP83820 only supports
31
31
C/BEN[3]
(MSB)
C/BEN[3]
(LSB)
Byte 3
Byte 0
(Continued)
Figure 3-2 Little Endian Byte Ordering
Figure 3-3 Big Endian Byte Ordering
24 23
24 23
C/BEN[2]
C/BEN[2]
Byte 2
Byte 1
16 15
16 15
10
3.2.1 Byte Ordering
The DP83820 can be configured to order the bytes of data
on the AD[31:0] bus to conform to Little Endian or Big
Endian ordering through the use of the CFG:BEM bit. Byte
ordering only affects bus mastered packet data transfers in
32-bit mode. Register information remains bit aligned (i.e.
AD[31] maps to bit 31 in any register space, AD[0] maps to
bit 0, etc.) when registers are accessed with 32-bit
operations. Bus mastered transfers of buffer descriptor
information also remain bit aligned.
When configured for Little Endian (CFG:BEM=0), the byte
orientation for receive and transmit data and descriptors in
system memory is as follows:
32-bit mode of operation. At the rising edge of RSTN, the
DP83820 samples the REQ64N pin to determine if the bus
is 64-bit capable. If the bus is not 64-bit capable, the
DP83820 will drive the 64-bit extension signals AD[63:32],
CBEN[7:4], and PAR64 to a low level to prevent the floating
inputs from causing significant current drain.
3.2.5 64-Bit Addressing
The DP83820 supports 64-bit addressing (Dual Address
Cycle) as a bus master for transferring descriptor and
packet data information. This mode can be enabled or
disabled through configuration from EEPROM. The
DP83820 also supports 64-bit addressing as a target.
3.3 Bus Operation
3.3.1 Target Read
A Target Read operation starts with the system generating
FRAMEN, Address, and either an IO read (0010b) or
Memory Read (0110b) command. See Figure 3-4. If the
32-bit address on the address bus matches the IO address
range specified in CFGIOA:IOBASE (for I/O reads) or the
memory address range specified in CFGMA:MEMBASE
(for memory reads), the DP83820 will generate DEVSELN
2 clock cycles later (medium speed).
The system must tri-state the Address bus, and convert the
C/BEN bus to byte enables, after the address cycle. On the
2nd cycle after the assertion of DEVSELN, all 32-bits of
data and TRDYN will become valid. If IRDYN is asserted at
that time, TRDYN will be forced HIGH on the next clock for
1 cycle, and then tri-stated.
C/BEN[1]
C/BEN[1]
Byte 1
Byte 2
8 7
8 7
C/BEN[0]
C/BEN[0]
(LSB)
(MSB)
Byte 0
Byte 3
0
0
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