DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 54

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.18 Wake Command/Status Register
The WCSR register is used to configure/control and monitor the DP83820 Wake On LAN logic. The Wake On LAN logic
is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the system if the
desired packet type, contents, or Link change are detected.
Note: Magic Packet is a trademark of Advanced Micro Devices, Inc.
20-11
bit
31
30
29
28
27
26
25
24
23
22
21
10
9
8
7
6
5
4
3
2
1
0
MCASTR
UCASTR
SOHACK
BCASTR
WKMAG
WKPAT3
WKPAT2
WKPAT1
WKPAT0
WKMCP
WKUCP
PHYINT
MPSOE
WKARP
WKBCP
WKPHY
PATM3
PATM2
PATM1
PATM0
ARPR
MPR
tag
Offset: 0040h
(Continued)
Magic Packet Received
Pattern 3 match
Pattern 2 match
Pattern 1 match
Pattern 0 match
ARP Received
Broadcast Received
Multicast Received
Unicast Received
Phy Interrupt
SecureOn Hack Attempt
Magic Pkt SecureOn Enable Enable Magic packet SecureOn feature. Only applicable when bit 8 is set. R/W
Wake on Magic Packet
Wake on Pattern 3 match
Wake on Pattern 2 match
Wake on Pattern 1 match
Wake on Pattern 0 match
Wake on ARP
Wake on Broadcast
Wake on Multicast
Wake on Unicast
Wake on Phy Interrupt
Tag: WCSR
description
Set to 1 if a Magic Packet has been detected and the WKMAG bit is set. RO,
cleared on read.
Associated bit set to 1 if a pattern 3 match is detected and the WKPAT3 bit is
set. RO, cleared on read.
Associated bit set to 1 if a pattern 2 match is detected and the WKPAT2 bit is
set. RO, cleared on read.
Associated bit set to 1 if a pattern 1 match is detected and the WKPAT1 bit is
set. RO, cleared on read.
Associated bit set to 1 if a pattern 0 match is detected and the WKPAT0 bit is
set. RO, cleared on read.
Set to 1 if an ARP packet has been detected and the WKARP bit is set. RO,
cleared on read.
Set to 1 if a broadcast packet has been detected and the WKBCP bit is set.
RO, cleared on read.
Set to 1 if a multicast packet has been detected and the WKMCP bit is set. RO,
cleared on read.
Set to 1 if a unicast packet has been detected the WKUCP bit is set. RO,
cleared on read.
Set to 1 if a Phy interrupt was detected and the WKPHY bit is set. RO, cleared
on read.
Set to 1 if the MPSOE and WKMAG bits are set, and a Magic Packet is
received with an invalid SecureOn password value. RO, cleared on read.
unused - returns 0
Enable wake on Magic Packet detection. R/W
Enable wake on match of pattern 3. R/W
Enable wake on match of pattern 2. R/W
Enable wake on match of pattern 1. R/W
Enable wake on match of pattern 0. R/W
Enable wake on ARP packet detection. R/W
Enable wake on broadcast packet detection. R/W
Enable wake on multicast packet detection. R/W
Enable wake on unicast packet detection. R/W
Enable wake on Phy Interrupt. The Phy interrupt can be programmed for Link
Change and a variety of other Physical Layer events. R/W
Access: Read Write
Size: 32 bits
54
usage
Hard Reset: 00000000h
Soft Reset: 00000000h
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