DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 11

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
If FRAMEN is asserted beyond the assertion of IRDYN, the
DP83820 will still make data available as described above,
but will also issue a Disconnect. That is, it will assert the
3.3.2 Target Write
A Target Write operation starts with the system generating
FRAMEN, Address, and Command (0011b or 0111b). See
Figure 3-5. If the upper 24 bits on the address bus match
CFGIOA:IOBASE (for I/O reads) or CFGMA:MEMBASE
(for memory reads), the DP83820 will generate DEVSELN
2 clock cycles later.
On the 2nd cycle after the assertion of DEVSELN, the
device will monitor the IRDYN signal. If IRDYN is asserted
C/BEN[3:0]
DEVSELN
FRAMEN
C/BEN[3:0]
AD[31:0]
DEVSELN
PERRN
TRDYN
FRAMEN
IRDYN
AD[31:0]
PERRN
TRDYN
PAR
IRDYN
CLK
PAR
CLK
Addr
Addr
(Continued)
Figure 3-5 Target Write Operation
Figure 3-4 Target Read Operation
11
STOPN signal with TRDYN. STOPN will remain asserted
until FRAMEN is detected as deasserted.
at that time, the DP83810 will assert TRDYN. On the next
clock the 32-bit double word will be latched in, and TRDYN
will be forced HIGH for 1 cycle and then tri-stated.
Note: Target write operations must be 32-bits wide.
If FRAMEN is asserted beyond the assertion of IRDYN, the
DP83820 will still latch the first double word as described
above, but will also issue a Disconnect. That is, it will assert
the STOPN signal with TRDYN. STOPN will remain
asserted until FRAMEN is detected as deasserted.
Data
Data
www.national.com