DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 14

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
3.4.5 Packet Recognition
The Receive packet filter and recognition logic allows
software to control which packets are accepted based on
destination address and packet type. Address recognition
logic includes support for broadcast, multicast hash, and
unicast addresses. The packet recognition logic includes
support for WOL, Pause, and programmable pattern
recognition.
3.5 Ethernet Media Access Controller (MAC)
The Media Access Control (MAC) unit performs the control
functions for the media access of transmitting and receiving
packets. During transmission, the MAC unit handles
building of frames and transmission of the frames over the
interface to the physical layer device. During reception,
data is received from the physical layer interface, the frame
3.5.1 Full Duplex Operation
Full duplex operation is the simultaneous transmission and
reception of packet data. In this mode of operation, receive
activity (CRS) is ignored in the decision making process for
transmission. During reception, collisions are also ignored.
To configure the DP83820 to operate in full duplex, set
TXCFG:CSI and TXCFG:HBI=1, and RXCFG:RX_FD = 1.
3.5.2 Full Duplex Flow Control
The DP83820 supports full duplex flow control using the
MAC Control Pause Frame as defined in the 802.3
specification. The packet recognition logic can detect
Pause frames, and cause the transmit MAC to pause the
correct number of slot times. In addition, the MAC can be
programmed to send Pause frames based on Rx FIFO
thresholds.
Flow Control operation is controlled by the Pause
Control/Status Register.
3.5.3 1000 Mb/s Operation
The DP83820 includes additional features to support 1000
Mb/s speed of operation. In this mode, the physical layer
interface is increased from 4-bit MII to 8-bit GMII (or 10-bit
TBI). In addition, features such as carrier extension and
frame bursting are required to meet the 802.3 specification
for 1000 Mb/s half-duplex operation.
3.6 Transmit MAC
The Transmit MAC implements the transmit portion of
802.3 Media Access Control. The Tx MAC retrieves packet
data from the Tx Buffer Manager and sends it out through
the transmit physical layer interface. Additionally, the Tx
MAC provides MIB control information for transmit packets.
The TX MAC supports 4-bit MII, 8-bit GMII, and 10-bit TBI
interfaces to physical layer devices
3.6.1 VLAN Tag Insertion
The Tx MAC has the capability to insert a 4-byte VLAN tag
in the transmit packet. If Tx VLAN Tag insertion is enabled,
preamble
7 bytes
1 byte
SFD dest addr
6 bytes
(Continued)
Figure 3-8 IEEE 802.3 Packet Structure
src addr
6 bytes
2 bytes
len
14
is checked for valid reception, and the data is transferred to
the receive FIFO. Control and status registers in the
DP83820 govern the operation of the MAC unit.
The standard 802.3 Ethernet packet consists of the
following fields: preamble, start of frame delimiter (SFD),
destination address, source address, length, data, frame
check sequence (FCS) and Extension (See Figure 3-8). All
fields are of fixed length except for the data field and
Extension. The Extension field is only used for 1000 Mb/s
half-duplex operation. During reception, the preamble and
SFD are stripped from the incoming packet. During
transmission, the DP83820 generates and prepends the
preamble and SFD. The FCS is normally appended by the
DP83820, but software may disable FCS inclusion on a
per-packet basis.
the MAC will insert the 4 bytes, as specified in the VTAG
register, following the source and destination addresses of
the packet. The VLAN tag insertion can be enabled on a
global or per-packet basis.
3.6.2 Carrier Extension
For 1000 Mb/s half-duplex operation it is necessary for
MAC to ensure that all valid carrier events exceed a
slotTime of 4096 bit times. To accomplish this, any transmit
event that is shorter than the slotTime will be extended
using Carrier Extension. On the GMII interface, this is
signaled to the Phy by TXER asserted with TXEN
deasserted and a TXD value of 0x0F.
3.6.3 Frame Bursting
The Tx MAC supports burst mode operation for 1000 Mb/s
half-duplex operation. This allows the device to transmit a
burst of packets without releasing control of the physical
medium. After a successful transmission, if additional
packets are available, the MAC will transmit a burst of
packets without allowing the medium to go idle. It does this
by inserting carrier extension between the frames. The
MAC will continue to burst frames as long as additional
packets are available in the internal FIFO and a burstLimit
of 65536 bit times has not been exceeded.
3.6.4 IP Checksum Generation
The Tx MAC supports task offloading of IP , TCP , and UDP
checksum generation. It can generate the checksums and
insert them into the packet. The checksum generation can
be enabled on a global or per-packet basis.
3.7 Receive MAC
This block implements the receive portion of 802.3 Media
Access Control. The Rx MAC retrieves packet data from
the receive portion and sends it to the Rx Buffer Manager.
Additionally, the Rx MAC provides MIB control information
and packet address data for the Rx Filter. The RX MAC
supports 4-bit MII, 8-bit GMII, and 10-bit TBI interfaces to
physical layer devices.
46 to 1500 bytes
data
4 bytes
fcs
<512 bytes
extension
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