DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 25

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
3.13.3.1 Transmit State Machine
The transmit state machine has the following states:
The transmit state machine manipulates the following internal data spaces:
Inputs to the transmit state machine include the following events:
txDescRead
txFIFOblock
txDescWrite
txFragRead
txDescRefr
state
txIdle
TxDescCache
txDescRead
txDescWrite
txFragRead
txDescRefr
txFifoBlock
txAdvance
txFifoAvail
CR:TXEN
txFifoCnt
XferDone
descCnt
FifoAvail
fragPtr
TXDP
CTDD
txIdle
(descCnt == 0) && !MORE
(descCnt == 0) && MORE
CR:TXEN && !CTDD
CR:TXEN && CTDD
XferDone && !OWN
XferDone && OWN
XferDone
XferDone
XferDone
FifoAvail
event
A 32- or 64-bit register that points to the current transmit descriptor. If priority queueing is
enabled, this points to the available transmit descriptor with the highest priority.
Current Transmit Descriptor Done. An internal bit flag that is set when the current transmit
descriptor has been completed, and ownership has been returned to the driver. It is cleared
whenever TXDP is loaded with a new value (either by the state machine, or the driver).
An internal data space equal to the size of the maximum transmit descriptor supported.
Count of bytes remaining in the current descriptor.
Pointer to the next unread byte in the current fragment.
Current amount of data in the txDataFifo in bytes.
Current amount of free space in the txDataFifo in bytes (size of the txDataFifo - txFifoCnt).
The transmit state machine is idle.
Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.
Waiting for the transfer of a complete descriptor from the PCI bus into the
TxDescriptorCache.
Waiting for free space in the TxDataFIFO to reach TxFillThreshold.
Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the
TxDataFIFO.
Waiting for the completion of the write of the cmdsts field of an intermediate transmit
descriptor (cmdsts.MORE == 1) to host memory.
(transitory state) Examine the link field of the current descriptor and advance to the next
descriptor if link is not NULL.
Driver asserts the TXEN bit in the command register. If priority queueing is enabled, this
corresponds to a specific priority queue.
Completion of a PCI bus transfer request.
TxFifoAvail is greater than TxFillThreshold.
(Continued)
Table 3-8 Transmit State Tables
txDescRead
txFIFOblock
txDescWrite
txFIFOblock
txFragRead
txDescRefr
next state
txAdvance
txAdvance
txAdvance
txIdle
25
start a burst transfer at address TXDP and a
length derived from TXCFG.
start a burst transfer to refresh the link field of the
current descriptor.
set ISR:TXIDLE.
start a burst transfer into the TxDataFIFO from
fragPtr. The length will be the minimum of
txFifoAvail and descCnt.
Decrement descCnt accordingly.
start a burst transfer to write the status back to the
descriptor, clearing the OWN bit.
write the value of TXDP to the txDataFIFO as a
handle.
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