DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 40

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.1 Command Register
This register is used for issuing commands to the DP83820. These commands are issued by setting the corresponding
bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are
provided here. Setting control bits to 0 has no effect, therefore there is no need for Read/modify/writes to this register.
100-1FCh
200-2FC
300-3FC
D0-DCh
F8-FCh
31-17
16-13
12-9
bit
CCh
ECh
E0h
E4h
E8h
F0h
F4h
8
7
6
5
RXPRI
TXPRI
TANLPAR TBI Auto-Negotiation Link Partner Ability Register
Registers
RST
RXR
SWI
TANAR
TANER
tag
Config.
TBICR
TBISR
CCSR
TESR
Offset: 0000h
(Continued)
Tag: CR
RX Priority Queue Select
TX Priority Queue Select
Reset
Software Interrupt
Receiver Reset
Clockrun Control/Status Register
Reserved
TBI Control Register
TBI Status Register
TBI Auto-Negotiation Advertisement Register
TBI Auto-Negotiation Expansion Register
TBI Extended Status Register
Reserved
Alias of 00-FCh (memory mapped only)
32-bit Read access of PCI Configuration Registers (memory mapped only)
Alias of 200-2FC. 32-bit Read access of PCI Configuration Registers (memory
mapped only)
description
Access: Read Write
unused
If Receive Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the RXE or RXD bits are set during a write
to this register. Bit 16 corresponds to Priority Queue 3 (highest priority),
while bit 13 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the RX Priority Queues.
If Transmit Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the TXE or TXD bits are set during a write
to this register. Bit 12 corresponds to Priority Queue 3 (highest priority),
while bit 9 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the TX Priority Queues.
Set to 1 to force the DP83820 to a soft reset state which disables the
transmitter and receiver, reinitializes the FIFOs, and resets all affected
registers to their soft reset state. This operation implies both a TXR and a
RXR. This bit will read back a 1 during the reset operation, and be cleared
to 0 by the hardware when the reset operation is complete.
Setting this bit to a 1 forces the DP83820 to generate a hardware interrupt.
This interrupt is mask-able via the IMR.
unused
When set to a 1, this bit causes the current packet reception to be aborted,
the receive data and status FIFOs to be flushed, and the receive state
machine to enter the idle state (RXE goes to 0). This is a write-only bit and
is always read back as 0.
Size: 32 bits
40
usage
Hard Reset: 00000000h
Soft Reset: 00000000h
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