DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 6

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

2.0 Pin Descriptions
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).
BIOS ROM/Flash Interface
MCSN
MD7, MD6,
MD5, MD4/EEDO,
MD3, MD2,
MD1/CFGDISN,
MD0/PMGDISN
MA15/TXD7,
MA14/TXD6,
MA13/TXD5,
MA12/TXD4,
MA11/TXD3,
MA10/TXD2,
MA9/TXD1,
MA8/TXD0,
MA7, MA6,
MA5, MA4/EECLK,
MA3/EEDI, MA2,
MA1, MA0
TXD7/MA15,
TXD6/MA14,
TXD5/MA13,
TXD4/MA12,
TXD3/MA11,
TXD2/MA10,
TXD1/MA9,
TXD0/MA8
TXEN/TXD8
TXER/TXD9
GTXCLK/
TXPMACLK
REF125
Symbol
Symbol
Pin No(s)
152,
151,
148,
147,
146,
145,
142,
141
153
154
140
137
Pin No(s)
104, 103,
102, 101,
114, 113,
112, 109,
108, 107,
106, 105
98, 97,
152,
151,
148,
147,
146,
145,
142,
141,
96,
95,
92
(Continued)
Direction
O
O
O
O
Direction
I
I/O
O
O
Gigabit Transmit Data: This is a group of 8 signals which are driven
synchronous to GTXCLK. TXD7 is the most significant bit.
Transmit Data: This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external PMD. TXD3 is the most significant
bit and TXD0 is the least significant bit. TXD7 through TXD4 are not used in this
mode
TBI Transmit Data: In TBI mode, this is the lower 8 bits of the 10-bit TBI
Transmit data.
BIOS ROM Address: During external BIOS ROM access, these signals
become part of the ROM address.
Transmit Enable: This signal is synchronous to TXCLK and provides precise
framing for data carried on TXD3-0 for the external PMD. It is asserted when
TXD3-0 contains valid data to be transmitted.
TBI Transmit Data: In TBI mode, this is TXD8 of the 10-bit TBI Transmit data.
Transmit Error: This signal is synchronous to TXCLK and provides error
indications and also is used for 1000 Mb/s half-duplex carrier extension and
packet bursting functions. The DP83820 will only assert this signal in 1000 Mb/s
mode of operation.
TBI Transmit Data: In TBI mode, this is TXD9 of the 10-bit TBI Transmit data.
GMII transmit Clock: A continuous clock used for 1000 Mb/s. It is output to an
external PMD and is the reference clock for Transmit GMII signaling. The clock
frequency is 125 MHz.
TBI Transmit Clock: In TBI mode, this is the 125MHz transmit clock to an
external PMD and is the reference for Transmit TBI signaling.
125 MHz Reference Clock: May be optionally connected to a 125 MHz
oscillator for 1000 Mb/s mode. If not used should be tied high.
BIOS PROM/Flash Chip Select: During a BIOS ROM/Flash access, this
signal is used to select the ROM device.
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these
signals are used to transfer data to or from the ROM/Flash device.
MD5:0 and MD7 pin pads have an internal weak pull up.
MD6 pin pad has an internal weak pull down.
BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these
signals are used to drive the ROM/Flash address.
6
Description
Description
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