DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 46

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXDESC3
RXDESC2
RXDESC1
RXDESC0
RXEARLY
RXRCMP
TXRCMP
RXSOVR
TXDESC
RXDESC
RXORN
RXIDLE
DPERR
SSERR
RMABT
TXURN
TXIDLE
RXERR
HIBINT
TXERR
RTABT
TXOK
RXOK
PME
PHY
SWI
MIB
(Continued)
Rx Descriptor for Priority
Queue 3
Rx Descriptor for Priority
Queue 2
Rx Descriptor for Priority
Queue 1
Rx Descriptor for Priority
Queue 0
Transmit Reset Complete
Receive Reset Complete
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Rx Status FIFO Overrun
High Bits Interrupt Set
Phy interrupt
Power Management Event
Software Interrupt
MIB Service
Tx Underrun
Tx Idle
Tx Packet Error
Tx Descriptor
Tx Packet OK
Rx Overrun
Rx Idle
Rx Early Threshold
Rx Packet Error
Rx Descriptor
Rx OK
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
Indicates that a requested transmit reset operation is complete.
Indicates that a requested receive reset operation is complete.
This bit is set whenever CFGCS:DPERR is set, but cleared (like all other
ISR bits) when the ISR register is read.
The DP83820 signaled a system error on the PCI bus.
The DP83820 received a master abort generated as a result of target not
responding.
The DP83820 received a target abort on the PCI bus.
Set when an overrun condition occurs on the Rx Status FIFO.
A logical OR of bits 22-16
Set to 1 when interrupt is generated due to change in phy status.
Set when WOL conditioned detected
Set whenever the SWI bit in the CR register is set.
Set when one of the enabled management statistics has reached its
interrupt threshold.
Set when a transmit data FIFO underrun condition occurs.
This event is signaled when the transmit state machine enters the idle state
from a non-idle state. This will happen whenever the state machine
encounters an "end-of-list" condition (NULL link field or a descriptor with
OWN clear).
This event is signaled after the last transmit descriptor in a failed
transmission attempt has been updated with valid status.
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated. If priority queueing is enabled, this bit will
be set when any of the TXDESC0-3 bits are set.
This event is signaled after the last transmit descriptor in a successful
transmission attempt has been updated with valid status
Set when a receive data FIFO overrun condition occurs.
This event is signaled when the receive state machine enters the idle state
from a running state. This will happen whenever the state machine
encounters an "end-of-list" condition (NULL link field or a descriptor with
OWN set).
Indicates that the initial Rx Drain Threshold has been met by the incoming
packet, and the transfer of the number of bytes specified by the DRTH field
in the RXCFG register has been completed by the receive DMA engine.
This interrupt condition will occur only once per packet.
This event is signaled after the last receive descriptor in a failed packet
reception has been updated with valid status.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated. If priority queueing is enabled, this bit will
be set when any of the RXDESC0-3 bits are set.
Set by the receive state machine following the update of the last receive
descriptor in a good packet.
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