PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 116

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure 65
3.8.3.2
The transmission of transparent frames (XTF command) is shown in
For transparent frames, the whole frame including address and control field must be
written to the XFIFOD. The host configures whether the CRC is generated and
appended to the frame (default) or not (selected in EXMD.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDCL frames (EXMD.ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling (collision resolution on the S bus) is required, the
signal must be set to idle (continuous ’1’s are transmitted). Reprogramming of ITF takes
effect only after the transmission of the current frame has been completed or after an
XRES command.
Figure 66
Data Sheet
Transmit
Frame
Transmit Transparent Frame
*
32 Bytes
1)
Transmit Frame Structure
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
WR
Transmission Sequence Example
Transmit Data Flow
(XTF)
XTF
XPR
32 Bytes
WR
32
FLAG
XTF
XPR
ADDRESS
ADDR
CPU Interface
IOM Interface
76 Bytes
116
12 Bytes
WR
XFIFO
CONTROL
XTF+XME
CTRL
32
Description of Functional Blocks
I
DATA
CHECKRAM
12
CRC
*
1)
XPR
Figure
ISAC-SX TE
fifoflow_tran.vsd
FLAG
PSB 3186
66.
2003-01-30
fifoseq_tran.vsd