PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 39

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.3
The layer-1 functions for the S/T interface of the ISAC-SX TE are:
– line transceiver functions for the S/T interface according to the electrical specifications
– conversion of the frame structure between IOM-2 and S/T interface;
– conversion from/to binary to/from pseudo-ternary code;
– level detection
– receive timing recovery for point-to-point, passive bus and extended passive bus
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– activation/deactivation procedures, triggered by primitives received over the IOM-2
– execution of test loops.
The wiring configurations in user premises, in which the ISAC-SX TE can be used, are
illustrated in
Data Sheet
of ITU-T I.430;
configuration
C/I channel or by INFO's received from the line;
S/T-Interface
Figure
15.
39
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30