PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 140

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

TMD
CIR0
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTAD corresponds to the last received HDLC frame; it is
4.1.17
Value after reset: 00
For general information please refer to
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
The setting of TLP is only valid if the IOM interface is active.
4.1.18
Value after reset: F3
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
Data Sheet
duplicated into RFIFOD for every frame (last byte of frame)
7
7
TMD -Test Mode Register D-Channel
CIR0 - Command/Indication Receive 0
0
H
H
0
CODR0
0
0
Chapter
140
CIC0
0
3.9.
CIC1
0
Detailed Register Description
S/G
0
0
0
BAS
TLP
ISAC-SX TE
RD/WR (29)
PSB 3186
2003-01-30
RD (2E)