PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 149

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MASKTR
ACFG2
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the TR_STA register.
SQC ... S/Q-Channel Change
A change in the received S-channel has been detected. The new code can be read from
the SQRxx bits of registers SQRR1-3 within the duration of the next multiframe (5 ms).
This bit is reset by a read access to the corresponding SQRRx register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the duration of the next multiframe (5 ms). This bit is reset by writing register SQXRx.
4.2.10
Value after reset: FF
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.11
Value after reset: 00
Note: Although no other Auxiliary Configuration Registers are supported by ISAC-SX
Data Sheet
TE, the name ACFG2 for this register was chosen intentionally in compliance with
ISAC-SX PEB3086.
7
7
MASKTR - Mask Transceiver Interrupt
ACFG2 - Auxiliary Configuration Register
1
0
H
H
1
0
0
1
1
0
149
ACL
LD
LED
RIC
Detailed Register Description
SQC
0
0
0
SQW
0
ISAC-SX TE
RD/WR (3D)
RD/WR (39)
PSB 3186
2003-01-30