PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 92

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

DU 1st byte value
DU 2nd byte value
e.g.
This identification sequence is usually done once, when the terminal is connected for the
first time. This function is used so that the software can distinguish between different
possible hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte and the principle of a read/
write access to a register is similar to the structure of the serial control interface
described in
read access the header 40
DD 1st byte value
DD 2nd byte value
DD 3rd byte value
DD 4th byte value
DD (nth + 3) byte value
All registers can be read back when setting the R/W bit in the byte for the command/
register address. The ISAC-SX TE responds by sending its IOM-2 specific address byte
(A1
Note: Application Hint:
3.7.3.5
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device. After 5 ms without reply the timer expires and the transmission
will be aborted with a EOM (End of Message) command by setting the MX bit to ’1’ for
two consecutive IOM-2 frames.
Data Sheet
h
) followed by the requested data.
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the m C has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the
ISAC-SX TE does not recognize an End of Reception.
000001
Monitor Time-Out Procedure
Chapter
ISAC-SX TE PSB 3186 V 1.4
3.2.1.1. For write access the header 43
H
R/W
1
0
/44
1
H
0
1
.
0
1
0
1
92
DESIGN
Header Byte
0
Register Address
0
Data 1
Data n
Description of Functional Blocks
0
0
0
H
0
/47
0
H
<IDENT>
can be used and for
0
ISAC-SX TE
PSB 3186
1
2003-01-30