PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 75

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

ISAC-SX TE
PSB 3186
Description of Functional Blocks
Figure 40
shows the timing of looping TSa from DU to DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
CDAxy
*)
µC
DD
TSa
TSa
*) if access by the µC is required
Figure 40
Data Access when Looping TSa from DU to DD
Figure 41
shows the timing of shifting data from TSa to TSb on DU (DD). In
Figure 41a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...9 and b ³ a+2 . In
Figure 41b)
shifting is done from one frame to the following
frame. This is the case when the timeslots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
75
2003-01-30