PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 205

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ISAC-SX
PEB 3086
Detailed Register Description
4.4.10
STI - Synchronous Transfer Interrupt
Value after reset: 00
H
7
0
STI
STOV
STOV
STOV
STOV
STI
STI
STI
STI
RD (58)
21
20
11
10
21
20
11
10
For all interrupts in the STI register the following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
The interrupts are automatically reset by reading the STI register. For general
information please refer to
Chapter
3.7.1.1.
STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles.
Data Sheet
205
2003-01-30