PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 56

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 23
LT-T mode
In this mode the frame relation between S/T interface and IOM-2 is flexible.
LT-S/NT mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
Note: In intelligent NT the D-channel access can be blocked by the IOM-2 D-channel
Data Sheet
NT -> TE
TE -> NT
FSC
DU
DD
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
handler.
B1
B1
F
B2 D
B2 D
F
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only)
B1
B1
E
Mapping of B-Channel Timeslots
1. Possibility
2. Possibility
D
D
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
B1
B1
E
D
D
B2
B2
E
E
56
B1
B1
D
F
D
B2 D
F
B2 D
B1
B1
E
Description of Functional Blocks
D
D
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
B1
B1
E
D
D
B2
line_iom_s_dch.vsd
PEB 3086
B2
E
E
2003-01-30
ISAC-SX
D
D