PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 215

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MODE2
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
After a reset pulse generated by the ISAC-SX and the corresponding interrupt (WOV or
CIC) the actual reset source can be read from the ISTA.
4.5.6
Value after reset: 00
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
Data Sheet
otherwise the watchdog timer expires and a reset pulse of 125 µs £ t £ 250 µs is
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
125 µs £ t £ 250 µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
7
MODE2 - Mode2 Register
0
H
0
0
0
215
INT_
POL
0
Detailed Register Description
0
0
PPSDX RD/WR (63)
PEB 3086
2003-01-30
ISAC-SX